1. Field of the Invention
The present invention generally relates to a semiconductor device and a method of forming the same.
Priority is claimed on Japanese Patent Application No. 2010-286647, filed Dec. 22, 2010, the content of which is incorporated herein by reference.
2. Description of the Related Art
In recent years, with the rapidly shrinking of the element sizes in DRAMs (dynamic random-access memories) and the like, the gate length in MOS transistors has become shorter. With the integration of a large number of MOS transistors into a memory cell region, the distance between adjacent MOS transistors also has been shortened. The shorter the gate length becomes, the greater is the problem of a worsening of transistor characteristics caused by the short-channel effect in the MOS transistors.
One proposed method for suppressing this type of MOS transistor short-channel effect is that of a buried-gate MOS transistor. According to a buried-gate MOS transistor, it is possible to physically and sufficiently achieve an effective channel length (gate length) and implement a microfine DRAM having a minimum process dimension of 60 nm or smaller.
In a buried-gate MOS transistor, a gate electrode (word line) is formed so as to be buried within a trench provided in a semiconductor substrate with an intervening gate insulating film, and the upper surface of the word line is formed so that it is at a position (lower-surface side) in the trench that is deeper than the upper surface of the semiconductor substrate. Also, an impurity diffusion layer is formed on one side of the word line and also on the other side thereof, this functioning as the source region or the drain region of the MOS transistor. By this constitution, if a drain voltage is applied to one of the impurity diffusion layers and the on potential is applied to the word line while maintaining the voltage on the other impurity diffusion, a channel is formed in the area peripheral to the word line within the semiconductor substrate, and the MOS transistor operates. These are disclosed in Japanese Patent Application Publication No. JPA 2001-210801.
A method for forming a word line (element separation region) for element separation that has the same structure as the word line of a MOS transistor is also known in Japanese Patent Application Publication No. JPA 2010-141170. According to a MOS transistor having this type of structure, because it is possible to achieve fine element separation, it is possible to implement a semiconductor device with a high level of integration.